Present digital-to-analog conversion techniques make use of various oversampling conversion techniques. These typically utilize a delta-sigma modulator in conjunction with conventional oversampling noise shaping techniques utilizing digital filters. Typically, an interpolation filter is utilized to increase the sample rate and then remove high frequency images at f.sub.s /2 and above, f.sub.s being the input sampling frequency. The interpolation filter provides a factor of 64.times. increase in the sampling rate. The delta-sigma modulator receives the output of the interpolation filter and converts the digital word into a one-bit digital data stream. This one-bit output controls a one-bit DAC, which converts the signal to a continuous time analog signal. This signal is then input to an analog low pass filter.
One disadvantage of the present delta-sigma modulator is the complexity thereof. These modulators are typically configured of a plurality of cascaded accumulators. The accumulators are formed with a register and an adder such that the overall modulator requires a plurality of additions to be performed and the results are then accumulated over time. However, the circuitry required to realize large order delta-sigma modulators is significant. This is primarily due to the complexity of the digital adder required in wide data path designs. There therefore exists a need for a more efficient circuit design for the delta-sigma modulator to reduce the amount of circuitry required to perform the multiple stages of integration.